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ILX528K
5000 x 3 pixel CCD Linear Sensor (Color)
Description The ILX528K is a reduction type CCD linear sensor developing for color DPPC. This sensor reads A3-size documents at a density of 400 DPI. Features * Number of effective pixels: 15000 pixels (5000 pixels x 3) * Pixel size: 8m x 8m (8m pitch) * Distance between line: 64m (8 lines) * Maximum data rate: 40MHz/color * Built-in clamp circuit * Ultra low lag/High sensitivity * Single 9V power supply * Input Clock Pulse: CMOS 5V drive * Number of output: 6 (2/color) * Package: 22pin DIP (400mil) Absolute Maximum Ratings * Supply voltage VDD * Operating temperature * Storage temperature Pin Configuration (Top View)
VOUT-ODD (G) VOUT-ODD (R) VOUT-EVEN (R) VDD NC 2 RS 2 CLP 1 22 GND
22 pin DIP (Cer-DIP)
Block Diagram
ROG
NC
13
12
VDD
14
CCD register (G) Read out gate (G) Sensor (G) Read out gate (G) CCD register (G)
CCD register (R) Read out gate (R) Sensor (R) Read out gate (R) CCD register (R)
CCD register (B) Read out gate (B) Sensor (B) Read out gate (B) CCD register (B)
1
1
1
1
16
8
2 3 4 5 6
21 VOUT-EVEN (G)
1
20 VOUT-EVEN (B)
1L
17
15
19 VOUT-ODD (B) 18 VREF
Output amplifier
Output amplifier
Output amplifier
Output amplifier
Output amplifier
Output amplifier
VREF
R
G
B
18
17 1 16 1
7 8 9
GND
15 1L 14 VDD 13 NC
22
VOUT-EVEN (G) 21
VOUT-EVEN (B) 20
VOUT-ODD (B) 19
GND 10
NC 11
12 ROG
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
-1-
VOUT-EVEN (R) 3
5000
5000
VOUT-ODD (G) 1
5000
VOUT-ODD (R) 2
E97307-PS
CLP
9
VDD
4
RS
7
NC
5
2
6
2
GND
11 -10 to +60 -30 to +80
V C C
11
NC
10
ILX528K
Pin Description Pin No. 1 2 3 4 5 6 7 8 9 10 11 Symbol VOUT-ODD (G) VOUT-ODD (R) VOUT-EVEN (R) VDD NC 2 RS 2 CLP GND NC Description Signal output (G) Signal output (R) Signal output (R) 9V power supply NC Clock pulse input Clock pulse input Clock pulse input Clock pulse input GND NC Pin No. 12 13 14 15 16 17 18 19 20 21 22 Symbol ROG NC VDD 1L 1 1 VREF VOUT-ODD (B) VOUT-EVEN (B) VOUT-ODD (G) GND Description Clock pulse input NC 9V power supply Clock pulse input Clock pulse input Clock pulse input Power supply (Clamp) Signal output (B) Signal output (B) Signal output (G) GND
Recommended Supply Voltage Item VDD Min. 8.55 Typ. 9 Max. 9.45 Unit V
Clock Characteristics Item Input capacity of 1, 2 Input capacity of 1L Input capacity of RS Input capacity of CLP Input capacity of ROG Symbol C1, C2 C1L CRS CCLP CROG Min. -- -- -- -- -- Typ. 900 60 60 60 10 Max. -- -- -- -- -- Unit pF pF pF pF pF
Clock Frequency Item 1, 2, 1L, RS, CLP Symbol f1, f2, f1L, fRS, fCLP Min. -- Typ. 1 Max. 20 Unit MHz
Input Clock Pulse Voltage Item 1, 2, 1L, RS, CLP, ROG Pulse Voltage High level Low level Min. 4.75 -0.3 Typ. 5.0 0 Max. 5.25 0.1 Unit V V
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ILX528K
Electrooptical Characteristics (Note 1) Ta = 25C, VDD = 9V, fRS = 1MHz, Input clock = 5Vp-p, Light source = 3200K, IR cut filter CM-500S (t = 1.0mm) Item Red Sensitivity Green Blue Sensitivity nonuniformity Saturation output voltage Red Saturation exposure Green Blue Dark voltage average Dark signal nonuniformity Image lag Supply current Total transfer efficiency Output impedance Offset level Dynamic range Symbol RR RG RB PRNU VSAT SER SEG SEB VDRK DSNU IL IVDD TTE ZO VOS DR Min. 1.19 2.17 1.47 -- 1 0.35 0.25 0.3 -- -- -- -- 92 -- -- 333 Typ. 1.7 3.1 2.1 5 1.5 0.68 0.48 0.58 1.5 1.5 0.02 45 98 170 4.4 1000 Max. 2.21 4.03 2.73 15 -- -- -- -- 3 5 -- 60 -- -- -- -- mV mV % mA % V -- Note 6 Note 6 Note 7 -- -- -- Note 8 Note 9 lx * s Note 5 % V Note 3 Note 4 V/(lx * s) Note 2 Unit Remarks
Notes 1) In accordance with the given electrooptical characteristics, the even black level is defined as the average value of D20, D22 to D118. The odd black level is defined as average value of D19, D21 to D117. 2) For the sensitivity test light is applied with a uniform intensity of illumination. 3) PRNU is defined as indicated below. Ray incidence conditions are the same as for Note 2. VOUT = 500mV PRNU = (VMAX - VMIN) /2 VAVE x 100 [%]
Where the 5000 pixels are divided to blocks of 100, even and odd pixels, respectively. The maximum output of each block is set to VMAX, the minimum output to VMIN and the average output to VAVE. 4) Use below the minimum value of the saturation output voltage. 5) Saturation exposure is defined as follows. SE = VSAT R
VOUT
6) Optical signal accumulated time int stands at 10ms. 7) VOUT = 500mV 8) Vos is defined as indicated bellow. VOUT indicates VOUT-EVEN (R), VOUT-ODD (R), VOUT-EVEN (G), VOUT-ODD (G), VOUT-EVEN (B), VOUT-ODD (B) 9) Dynamic range is defined as follows. DR =
VOS
VSAT GND VDRK When the optical signal accumulated time is shorter, the dynamic range gets wider because the optical signal accumulated time is in proportion to the dark voltage. -3-
Clock Timing Chart 1
ROG
5
0
1
2
1
5
1L
0
2
5
0
RS
5
0
S3
D3
D19
D117
D5
D21
D119
S4997
S1
S4999
D1
D17
D115
VOUT-ODD (R) VOUT-ODD (G) VOUT-ODD (B)
S4
S4995
D121 S4998 S5000 D122
D4
D20
D118
D6
D22
D120
D2
D18
D116
S2
VOUT-EVEN (R) VOUT-EVEN (G) VOUT-EVEN (B) Optical black (100 pixels) Dumy signal (120 pixels)
Effective picture elements signal (5000 pixels)
1-line output period (5124 pixels) ILX528K
Note) The transfer pulses (1, 2, 1L) must have more than 2562 cycles.
S4996
D124
D123
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CLP
5
0
3
2562
ILX528K
Clock Timing Chart 2
t4 t5
ROG t6 1 1L
t2 t7
t1
t3
2
Clock Timing Chart 3
t7 1 1L t6
2
t11
t8
t10
t9
RS t12 CLP t13 t17 VOUT t15 t14 t18 t16
-5-
ILX528K
Clock Timing Chart 4
Cross point 1 and 2 1 5V
1.5V (Min.) 2 0V
1.5V (Min.)
Cross point 1L and 2 2 5V
2.0V (Min.) 1L 0V
0.5V (Min.)
Clock Pulse Recommended Timing Item ROG, 1 pulse timing ROG pulse high level period ROG, 1 pulse timing ROG pulse rise time ROG pulse fall time 1 pulse rise time /2 pulse fall time 1 pulse fall time /2 pulse rise time RS pulse rise time RS pulse fall time RS pulse high level period RS, 1L pulse timing RS, CLP pulse timing CLP pulse rise time CLP pulse fall time CLP pulse high level period CLP 1L pulse timing Signal output delay time Symbol Min. 50 600 400 0 0 0 0 0 0 10 0 0 0 0 10 5 -- -- Typ. 100 1000 1000 5 5 5 5 5 5 2001 5 5 5 5 2001 1001 12 12 Max. -- -- -- 10 10 10 10 10 10 -- -- -- 10 10 -- -- -- -- Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18
1 These timing is the recommended condition under fRS = 1MHz. -6-
Application Circuit
VOUT-EVEN (G) VOUT-EVEN (B) VOUT-ODD (B) IC1 Buffer1 Buffer1 3.3F /16V 18 17 16 15 14 12 13 2 2 100 100
1 ROG
1
1L
Buffer1
22 21 20
19
1
1
1L
GND
VREF
VDD
NC
VOUT-ODD (B)
9V 2 3 8 4 5 7 6 9
VOUT-ODD(G)
VOUT-ODD (R) VOUT-EVEN (G)
VOUT-EVEN (R) VOUT-EVEN (B)
VDD
NC
2
RS
2
CLP
1
10
GND
11
Buffer1
2
100
2
100 Buffer1 : IC1 100 IN 9V IC1 : 74AC04
Buffer1
0.1F
47F/16V Buffer1
NC
ROG
-7-
2 RS 2 CLP
VOUT-EVEN (R) VOUT-ODD (R) VOUT-ODD (G)
2SC2785 OUT 5.1k
Data rate fRS = 1MHz.
ILX528K
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
ILX528K
Example of Representative Characteristics (VDD = 9V, Ta = 25C)
Spectral sensitivity characteristics (Standard characteristics)
1.0
0.8
Relative sensitivity
0.6
0.4
0.2
0.0 400
450
500
550 Wavelength [nm]
600
650
700
Dark voltage rate vs. Ambient temperature (Standard characteristics)
100 10
Output voltage rate vs. Integration time (Standard characteristics)
Dark voltage rate
10
Output voltage rate
0 10 20 30 40 50 60
1
1
0.1 -10
0.1 1 5 int - Integration time [ms] 10 Ta - Ambient temperature [C]
Offset level vs. Supply voltage (Standard characteristics)
10 10
Offset level vs. Ambient temperature (Standard characteristics)
8
8
VOS - Offset level [V]
6
VOS - Offset level [V]
8.5 9.0 VDD - Supply voltage [V] 9.5
6
4
4
2
2
0
0 -10
0
10
20
30
40
50
60
Ta - Ambient temperature [C]
-8-
ILX528K
Notes of Handling 1) Static charge prevention CCD image sensors are easily damaged by static discharge. Before handling be sure to take the following protective measures. a) Either handle bare handed or use non chargeable gloves, clothes or material. Also use conductive shoes. b) When handling directly use an earth band. c) Install a conductive mat on the floor or working table to prevent the generation of static electricity. d) Ionized air is recommended for discharge when handling CCD image sensor. e) For the shipment of mounted substrates, use boxes treated for prevention of static charges. 2) Notes on Handling CCD Cer-DIP Packages The following points should be observed when handling and installing cer-DIP packages. a) Remain within the following limits when applying static load to the ceramic portion of the package: (1) Compressive strength: 39N/surface (Do not apply load more than 0.7mm inside the outer perimeter of the glass portion.) (2) Shearing strength: 29N/surface (3) Tensile strength: 29N/surface (4) Torsional strength: 0.9Nm
Upper ceramic layer 39N 29N 29N 0.9Nm
Lower ceramic layer
(1)
Low-melting glass
(2)
(3)
(4)
b) In addition, if a load is applied to the entire surface by a hard component, bending stress may be generated and the package may fracture, etc., depending on the flatness of the ceramic portion. Therefore, for installation, either use an elastic load, such as a spring plate, or an adhesive. c) Be aware that any of the following can cause the glass to crack: because the upper and lower ceramic layers are shielded by low-melting glass, (1) Applying repetitive bending stress to the external leads. (2) Applying heat to the external leads for an extended period of time with soldering iron. (3) Rapid cooling or heating (4) Rapid cooling or impact to a limited portion of the low-melting glass with a small-tipped tool such as tweezers. (5) Prying the upper or lower ceramic layers away at a support point of the low-melting glass. Note that the preceding notes should also be observed when removing a component from a board after it has already been soldered. 3) Soldering a) Make sure the package temperature does not exceed 80C. b) Solder dipping in a mounting furnace causes damage to the glass and other defects. Use a grounded 30W soldering iron and solder each pin in less then 2 seconds. For repairs and remount, cool sufficiently. c) To dismount an imaging device, do not use a solder suction equipment. When using an electric desoldering tool, ground the controller. For the control system, use a zero cross type.
-9-
ILX528K
4) Dust and dirt protection a) Operate in clean environments. b) Do not either touch glass plates by hand or have any object come in contact with glass surfaces. Should dirt stick to a glass surface, blow it off with an air blower. (For dirt stuck through static electricity ionized air is recommended.) c) Clean with a cotton bud and ethyl alcohol if the glass surface is grease stained. Be careful not to scratch the glass. d) Keep in a case to protect from dust and dirt. To prevent dew condensation, preheat or precool when moving to a room with great temperature differences. 5) Exposure to high temperatures or humidity will affect the characteristics. Accordingly avoid storage or usage in such conditions. 6) CCD image sensors are precise optical equipment that should not be subject to mechanical shocks. 7) Note that the normal output signal is not obtained immediately after the device power is turned on.
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Package Outline
Unit: mm
22pin DIP (400mil)
55.7 0.5
40.0 (8m x 5000Pixels)
22 12
5.0 0.5
1 54.2 11
4.0 0.5
0.3
M
1. The height from the bottom to the sensor surface is 2.38 0.3mm. 2. The thickness of the cover glass is 0.7mm, and the refractive index is 1.5.
PACKAGE STRUCTURE
PACKAGE MATERIAL
Cer-DIP
LEAD TREATMENT
TIN PLATING
LEAD MATERIAL
42 ALLOY
PACKAGE WEIGHT
7.1g
3.58 4.28 0.5
2.54
0.51
(AT STAND OFF) 10.16
0.25
H
9.0 10.0 0.5
V
No.1 Pixel (Green)
0 to 9
9.52 0.5
- 11 -
ILX528K

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